The present disclosure is related to the field of semiconductor device manufacturing and packaging. More specifically but not exclusively, the present disclosure is related to grinding of semiconductor wafers having low-K interlayer dielectric (ILD) layers.
The desire for thinner wafers and enhanced performance of integrated circuits has led to the integration of low-K (low-dielectric constant) interlayer dielectrics into semiconductor devices. Low-K dielectrics have lower dielectric constant values than materials such as silicon dioxide (K ˜4) and thus are able to reduce the capacitance between metal interconnects on a chip or integrated circuit die, allowing faster and smaller integrated circuits. The use of low-K dielectrics as insulators in semiconductor wafers, however, creates difficulties during wafer packaging assembly operations. For example, grinding of low-K wafers using conventional wafer grinding processes has proven impractical because low-K dielectrics display poor adhesion and fragility. Additionally, wafer sawing may be difficult because cracks often propagate from the dicing saw through the wafer and into the integrated circuit.